NT5CC128M16IP-DI DDR3 Memory Chip - High-Speed Data Transfer and Advanced Features for Data Integrity and Power Savings

The NT5CC128M16IP-DI is a DDR3 memory chip designed for use on the Antminer S9 control board. With an 8n prefetch architecture and differential clock and data strobe, this chip enables high-speed double data transfer rates of up to 1866Mb/sec/pin for general-purpose applications. The chip is internally configured as eight banks of DRAM, and 2Gb chips are organized as 32Mbit x 8 I/O x 8 bank or 16Mbit x 16 I/O x 8 bank devices. The NT5CC128M16IP-DI is compliant with JEDEC DDR3 and is designed to meet all key DDR3(L)DRAM key features.

Key Features, Benefits, and Applications

All control and address inputs are synchronized to a pair of externally supplied differential clocks, and all I/Os are source synchronous with single-ended DQS or differential DQS pairs.

In addition to its high-speed operation, the NT5CC128M16IP-DI offers a range of features designed to ensure data integrity, power savings, and signal integrity. Automatic Self-Refresh (ASR)TS with built-in DRAM, Auto Refresh and Self Refresh Mode, Partial Array Self Refresh (PASR), and power down mode all work together to optimize power usage. Configurable DS for system compatibility, configurable on-chip termination, and ZQ calibration for DS/ODT impedance accuracy via external ZQ pads (240 ohms ±1%) ensure signal integrity. Write leveling via MR settings and read leveling via MPR ensure signal synchronization. The NT5CC128M16IP-DI is also designed with SSTL_15 for DDR3 (VDD/VDDQ=1.5V(±0.075V)) and SSTL_1353 for DDR3L (VDD/VDDQ=1.35V(-0.067/+0.1V)) interfaces and power supply.

Key Features:

• Compliant with JEDEC DDR3
• 8n Prefetch Architecture
• Differential Clock and Data Strobe
• Double Data Rate on DQ, DQS and DM
• Automatic Self-Refresh (ASR)TS with Built-In DRAM
• Auto Refresh and Self Refresh Mode
• Partial Array Self Refresh (PASR)
• Power Down Mode Configurable DS for System Compatibility
• Configurable On-Chip Termination
• ZQ Calibration for DS/ODT Impedance Accuracy via External ZQ Pads (240 ohms ±1%)
• Write Leveling via MR Settings
• Read Leveling via MPR
• SSTL_15 for DDR3: VDD/VDDQ=1.5V(±0.075V)
• SSTL_1353 for DDR3L: VDD/VDDQ=1.35V(-0.067/+0.1V)

Application:

• Antminer S9 Control Board
• Other General-Purpose Applications Requiring High-Speed Data Transfer